1. Field of the Invention
The present invention relates to a digital filter for use in a digital audio equipment or the like, and more particularly to a synthesizing filter or a separation filter which uses a QMF (Quadrature Mirror Filter).
2. Description of the Related Art
Recently, digital audio equipment has enjoyed increasing popularity with the consuming public, due in part to digital filter technology's remarkably clear and crisp audio sound. This type of technology is typified by the increasingly common compact disk player. An analog filter handles analog signals, whereas a digital filter handles digital signals. One great advantage that digital filters have over analog filters is that the filter characteristics of the digital filter are easily modified. This is especially helpful where complicated filtering is required, since the digital filter's filtering characteristics will not easily vary due to changes in the filter's external surroundings or due to effects caused by the passage of time.
Digital filters are classified into an FIR (Finite Impulse Response) filters and IIR (Infinite Impulse Response) filters.
Since the FIR filter computes sequential output data using only old sequential input data, the influence of the sequential input data's determined impulse response on sequential output data is limited to finite time. Since the IIR filter feeds old sequential output data back to the input side and treats this data as new sequential input data to compute sequential output data, the influence of the impulse response of the sequential input data on the sequential output data extends to infinite time. The FIR filter and IIR filter are used for the same purpose. Although the IIR filter has higher performance, the design is difficult and the structure is complicated. In this respect, the FIR filter is used more widely.
The FIR filter is designed in such a way as to obtain sequential output data y(n) through convolution of the sequential input data x(n) and the impulse response, as apparent from an equation (1) where h(k) is a filter coefficient (weighting function) and N is the number of taps being considered. ##EQU1## Performing a Z transform of the equation (1) yields an equation (2). An equation (3) is derived as the complex frequency response from the equation (2), with the frequency response being further derived in equation (3). ##EQU2## Substituting .omega.=2.pi.k/N in the equation (3) yields an equation (4). ##EQU3## The equation (4) can be considered as an equation for discrete Fourier transform (DFT). Thus, the filter coefficient h(k) is obtained by inverse discrete Fourier transform (IDFT) of the frequency response given by the equation (4).
The block diagram illustrated in FIG. 18 shows the structure of a typical FIR filter.
A plurality of delay elements 101, connected in series, are each constituted by a shift register and sequentially delay the sequential input data x(n) by a given time (T). Each of a plurality of multipliers 102, connected to the outputs of the respective delay elements 101, multiplies the output of the associated delay element 101 by a filter coefficient h(k). Accordingly, convolution of the sequential input data x(n) and the impulse response is performed. A total adder 103 obtains the sum of the outputs of the individual multipliers 102 (the outputs of the individual delay elements 101 each multiplied by a predetermined filter coefficient h(k)), and outputs the sum as sequential output data y(n). This operation corresponds to a solution of the convolution expressed in equation (1).
The FIR filter shown in FIG. 18, however, has a shortcoming that the circuit scale increases with an increase in the number of taps N.
As a solution to this problem, a stored program type FIR filter as shown in FIG. 19 has been proposed.
A RAM (Random Access Memory) 111 stores sequential input data x(n) in the order with which they are input. A ROM (Read Only Memory) 112 holds a plurality of filter coefficients h(k). When accessed, the ROM 112 outputs a specific filter coefficient h(k) in accordance with the value of k which increases every step. It is to be noted that k is the same as k in the equation (1). A multiplier 113 multiplies the sequential input data x(n-k), read from the RAM 111, by the filter coefficient h(k), read from the ROM 112. An accumulator 114, which comprises an adder 115 and a register 116, accumulates the result of the multiplication done by the multiplier 113. That is, the adder 115 adds the output of the multiplier 113 and the output of the register 116, and stores the addition result again in the register 116, thereby sequentially accumulating the multiplication result from the multiplier 113. A register 117 receives the accumulation result output from the accumulator 114, and outputs it as sequential output data y(n).
The stored program type FIR filter shown in FIG. 19 reads the sequential input data x(n) and the filter coefficient h(k) respectively from the RAM 111 and ROM 112 in order, and repeatedly performs a multiplication and addition operation to derive a product and sum, corresponding to the sequential output data y(n) represented by equation (1). With this type of filter, even if the number of taps N increases, the circuit scale will not increase.
Incidentally, from the frequency response, an FIR filter with a filter coefficient h.sub.2 (n), which satisfies an equation (5), is called a mirror filter to an FIR filter with a filter coefficient h.sub.1 (n). EQU h.sub.2 (n)=(-1).sup.n h.sub.1 (n) (5)
The relation of Z transform of the mirror filter is given by an equation (6). ##EQU4## When the frequency response is considered, an equation (8) can be derived from an equation (7). EQU h.sub.2 (n)=e.sup.j.pi.n h.sub.1 (n) (7) EQU H.sub.2 (e.sup.j.omega.)=H.sub.1 (e.sup..omega.+.pi.) (8)
It is understood from the equation (8) that the frequency response of the mirror filter is .pi./2 and is consequently symmetrical. As .pi./2 is 1/4 of the sampling frequency, this mirror filter is called quadrature mirror filter (QMF). The details of this QMF are given in IEEE TRANSACTIONS 0N ACOUSTICS, SPEECH, AND SIGNAL PROCESSING, VOL. ASSP-32, NO. 3, JUNE 1984, pp. 522-531.
QMFs are classified to a separation filter and a synthesizing filter.
The separation filter separates one piece of sequential input data to plural pieces of sequential output data, and splits the frequency component to subbands. The synthesizing filter synthesizes plural pieces of sequential input data into a single piece of sequential output data, i.e., synthesizes the frequency components in a plurality of subbands into a single frequency component.
The separation filter is designed in such a way as to provide two sequential output data y.sub.a (n) and y.sub.b (n), which are sequential input data x(n) separated by a convolution of the sequential input data x(n) and the impulse response and by the addition of those two or subtraction of one from the other, as apparent from equations (9) and (10). ##EQU5## FIG. 20 shows the structure of a typical separation filter.
A plurality of delay elements 121, connected in series, sequentially delay the sequential input data x(n) by a given time (T). Each of multipliers 122, connected to the outputs of those delay elements 121 at even-numbered stages, multiplies the output of the associated delay element 121 by a filter coefficient h(2k) and sends the result to a total adder 123. Each of multipliers 124, connected to the outputs of those delay elements 121 at odd-numbered stages, multiplies the output of the associated delay element 121 by a filter coefficient h(2k+1) and sends the result to a total adder 125. Accordingly, convolution of the sequential input data x(n) and the impulse response is performed. The total adder 123 obtains the sum of the outputs of the individual multipliers 122 (the outputs of the individual delay elements 121 each multiplied by a predetermined filter coefficient h(2k)), and outputs the sum as data An. The total adder 125 obtains the sum of the outputs of the individual multipliers 124 (the outputs of the individual delay elements 121 each multiplied by a predetermined filter coefficient h(2k+1)), and outputs the sum as data Bn. A subtracter 126 subtracts the data Bn, output from the total adder 125, from the data An, output from the total adder 123, and outputs the result as sequential output data y.sub.a (n). An adder 127 adds the data An from the total adder 123 and the data Bn from the total adder 125 together, and outputs the result as sequential output data y.sub.b (n).
The separation filter shown in FIG. 20, however, has a shortcoming that the circuit scale increases with an increase in the number of taps N. Particularly, in separating one piece of sequential input data to three or more pieces of sequential output data, the above-described separation filter should be multiplexed, thus further increasing the circuit scale.
The synthesizing filter is designed in such a way as to provide sequential output data y(2n) and y(2n+1), which are two pieces of sequential input data x.sub.a (n) and x.sub.b (n) synthesized, through convolution of those sequential input data x.sub.a (n) and x.sub.b (n) and the impulse response and their addition or subtraction, as apparent from equations (11) and (12). ##EQU6## FIG. 21 shows the structure of a typical synthesizing filter 130.
A subtracter 131 subtracts the sequential input data x.sub.b (n) from the sequential input data x.sub.a (n). An adder 132 adds the sequential input data x.sub.b (n) and the sequential input data x.sub.a (n) together. A switch 133 alternately switches between the output of the subtracter 131 and the output of the adder 132, and outputs the selected output to series-connected delay elements 121. Then, the convolution of the result of the subtraction of the sequential input data x.sub.b (n) from the sequential input data x.sub.a (n), the result of the addition of x.sub.a (n) and x.sub.b (n) and the impulse response is executed by multipliers 122 and 124 and total adders 123 and 125, which are designed in the same way as those of the separation filter shown in FIG. 20. The switch 134 performs alternate switching between the outputs of the total adders 123 and 125 in synchronism with the switch 133, and outputs the selected output as sequential output data y(2n) or y(2n+1).
The synthesizing filter 130 shown in FIG. 21, however, has a shortcoming that the circuit scale increases with an increase in the number of taps N. Particularly, in synthesizing three or more pieces of sequential input data into one piece of sequential output data, the synthesizing filter 130 shown in FIG. 21 should be multiplexed, thus further increasing the circuit scale.
For instance, in synthesizing three pieces of sequential input data x.sub.a (n), x.sub.b (n) and x.sub.c (n), first, two pieces of sequential input data x.sub.a (n) and x.sub.b (n) are synthesized by a synthesizing filter 130.alpha., yielding data z(2n) and z(2n+1), as shown in FIG. 22. Then, the data z(2n) and z(2n+1) and the sequential input data x.sub.c (n) are synthesized by a synthesizing filter 130.beta., yielding sequential output data y(4n) and y(4n+1). It is apparent that synthesizing three pieces of sequential input data requires two synthesizing filters 130.
There may be a case where three pieces of sequential input data x.sub.a (n), x.sub.b (n) and x.sub.c (n) are sent in parallel, and the sequential input data x.sub.c (n) is input to the synthesizing filter 130.beta. with a delay corresponding to the processing time of the synthesizing filter 130.alpha.. In this case, a delay circuit 40 should be provided separately from the two synthesizing filters 130.alpha. and 130.beta., so that the sequential input data x.sub.c (n) will be input via this delay circuit 140 to the synthesizing filter 130.beta., as shown in FIG. 23. This design undesirably increases the circuit scale by the delay circuit 140.
In synthesizing four pieces of sequential input data x.sub.a (n), x.sub.b (n), x.sub.c (n) and x.sub.d (n), first, two pieces of sequential input data x.sub.a (n) and x.sub.b (n) are synthesized by a synthesizing filter 130.alpha., yielding data z.sub.a (2n) and z.sub.a (2n+1), as shown in FIG. 24. At the same time, two pieces of sequential input data x.sub.c (n) and x.sub.d (n) are synthesized by a synthesizing filter 130.gamma., yielding data z.sub.b (2n) and z.sub.b (2n+1). Then, the data z.sub.a (2n), z.sub.a (2n+1), z.sub.b (2n) and z.sub.b (2n+1) are synthesized by a synthesizing filter 130.beta., yielding sequential output data y(4n) and y(4n+1). Thus, when four pieces of sequential input data are synthesized, three synthesizing filters 130 are required.
As is apparent from the above, synthesizing of three or more pieces of sequential input data needs a plurality of synthesizing filters 130 for the multiplexing purpose, thus significantly increasing the overall circuit scale.